[address-policy-wg] Re: Fallacy by Kurt (was Re: IPv6 PolicyClarification - Initial allocation criteria "d)")
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Andre Oppermann
oppermann at pipeline.ch
Tue Jun 22 14:28:39 CEST 2004
Masataka Ohta wrote: > > Oliver Bartels: > > >>So that would be a maximum of 10.000 routing table entries (if we > >>can manage to keep it at "1 prefix per LIR"). > > > > Full Ack. > > > > A table of this size is handled with a one cycle memory access > > in modern routing hardware. > > By definition of "one cycle memory access", any table of any size > can be handled with a one cycle memory access in any routing hardware. > > However, memory access cycle can be a lot larger than a CPU clock > cycle. > > On typical modern chips, tens of registers can be accessed within > a CPU cycle. On chip primary cache with thousands of entries > needs about twice or three times more than that. Off chip cache > needs about ten, twenty or, maybe, hundred more to access. If I get this correctly you seem to argue that because todays hardware is "slow" and/or "inefficient" for large routing tables IPv6 multi- homing should not be allowed? This way at looking things in fundamentally broken. The need for speed has started many developments we enjoy today. I am sure engineers will find good and efficient ways to deal with large routing tables at high speeds. Just look at the last ten years. In 1994 a T3 was like "wow!". Today n-times 10Gig is "wow!". Go ahead and technology will follow. -- Andre
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