[address-policy-wg] Re: Fallacy by Kurt (was Re: IPv6 Policy Clarification - Initial allocation criteria "d)")

On Tue, 22 Jun 2004 21:26:30 +0900, Masataka Ohta wrote:
>However, memory access cycle can be a lot larger than a CPU clock
>cycle.
With 10000 prefixed put in in a TCAM and get a result per pipeline
cycle. This means 100M packet lookups per second, which is
sufficient for >10G. TCAM does the complete prefix lookup
in one cycle. It's limit by price is the table size (typically 64K to 256K).
If it is combined with regular RAM (per cluster table), someone can
select millions of prefixes *pipelined* within few accesses in
a fully pipelined architecture in the >=10G and >=100Mpps range.

>On typical modern chips, tens of registers can be accessed within
>a CPU cycle. On chip primary cache with thousands of entries
>needs about twice or three times more than that. Off chip cache
>needs about ten, twenty or, maybe, hundred more to access.
Modern Routers no longer use traditional CPU/cache architectures.
Either fast static RAM together with trie structures (e.g. patricia
tree/radix tree) or TCAM is used together with highly pipelined
processors.

Best Regards
Oliver Bartels



Oliver Bartels F+E + Bartels System GmbH + 85435 Erding, Germany
oliver at bartels.de + http://www.bartels.de + Tel. +49-8122-9729-0